In recent years, it is expected that it is possible to realize a high performance and cheap optical interconnect device by manufacturing an optical integrated circuit using the process technology for a silicon Complementary Metal Oxide Semiconductor (CMOS) circuit. It is a photodetector that is in one of devices indispensable to the optical integrated circuit. The photodetector is desirable to be high-speed and sensitive, with short optical absorption length and small in size. From a point of view of the cost and yield, a photodiode using SixGe1-x (0≦x≦1) which can be monolithically integrated with a Si waveguide is considered promising.
For example, a waveguide detector using poly germanium stacked on a silicon on Insulator (SOI) substrate is disclosed in the patent literature 1.
Also, the nonpatent literature 1 discloses a process for forming a Ge layer having low defect density by performing selective epitaxial growth of a Ge layer in a trench part of SiO2 film using a Si layer as an underlayer, and further performing lateral overgrowth of the Ge layer on the SiO2 film.    Patent Literature 1: Japanese Patent Laid-Open Application Publication (Translation of PCT Application) No. 2006-522465 (paragraphs [0030], [0018], FIG. 5)    NonPatent Literature 1: J. S. Park et al., Low-Defect-Density Ge Epitaxy on Si(001) Using Aspect Ratio Trapping and Epitaxial Lateral Overgrowth, Electrochemical and Solid-State Letters 12 p. 142 (2009) (FIG. 1).